Vinayak Nair/ AEROSPACE

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Verified baselineC++17 flight core + Python ground tooling

ASTRA-OS

FLIGHT SOFTWARE · COMMAND / TELEMETRY · FDIR · ASSURANCE · RASPBERRY PI

ASTRA-OS is a C++17 flight-software testbed for command validation, telemetry, mode management, FDIR, fault injection and requirements-based verification.

Illustration of the ASTRA-OS flight and ground software topology.

01Evidence you can inspect

The architecture, telemetry timelines and assurance counts below come directly from the public repository. The interactive console is labeled separately because it is a browser model of the documented state machine, not the native C++ executable.

Native tests20/20CTest suites passed
Current tree35/35Python / browser tests
Fault policy10/10FDIR cases passed
Traceability0Requirement failures
Current-tree snapshot: 4150e97; frozen reports retain their tested-commit counts.Pinned sourceEvidence guide
ASTRA-OS diagram connecting ground commands, protocol validation, execution policy, deterministic flight software, telemetry and the verification pipeline.
Implemented architecture

Flight, ground and assurance flow

Command decoding, replay/freshness guards and execution authorization are separate boundaries before state mutation. Telemetry and provenance-bound verification close the loop around the deterministic flight core.

Open source diagram
Telemetry sequence showing ASTRA-OS transition from BOOT to NOMINAL, into DEGRADED_PAYLOAD, and back to NOMINAL.
Recorded telemetry

Mode response timeline

The preserved demo sequence leaves BOOT for NOMINAL, enters DEGRADED_PAYLOAD on the injected CPU-overload path, then returns to NOMINAL after fault clear and an accepted SET_MODE command.

Open source timeline
Telemetry sequence showing a CPU_OVERLOAD fault interval followed by a cleared NONE state.
Recorded telemetry

Fault-state timeline

The same sequence makes the injected CPU_OVERLOAD interval and subsequent clear visible in telemetry. This is a software-policy response, not proof of every physical detector or recovery mechanism.

Open source timeline
Browser behavior model

Exercise the state machine

Use the public console to issue documented commands and faults and observe modeled mode, fault and telemetry responses. It is intentionally not described as WebAssembly, the native executable or a live Raspberry Pi session.

02Problem

Writing a mode manager or UDP packet parser is easy to demonstrate. Showing that the software rejects the wrong command, enters a safe state on the right fault, bounds recovery attempts, preserves event history and remains traceable to requirements is the harder engineering problem.

ASTRA-OS treats that verification chain as part of the product rather than a report written after implementation.

03Architecture

Flight segment
  • Eight deterministic operating modes
  • Health and watchdog monitoring
  • FDIR with simultaneous-fault priority
  • Bounded recovery supervision
  • Rate-group scheduler and typed event logging
  • Binary command and telemetry packets
Ground / assurance segment
  • Python command sender and telemetry decoder
  • YAML-driven deterministic scenarios
  • Fault injection and FDIR campaign
  • Seeded Monte Carlo regression
  • Protocol-conformance and requirement gates
  • Sanitizer, static-analysis, mutation and fuzz checks

The command path explicitly distinguishes packet integrity, freshness/replay policy, execution authorization and semantic validation. CRC detects corruption in the tested model; it is not presented as cryptographic authentication.

04Current assurance campaign

20/20
Native CTest
8/8
Scenarios
10/10
FDIR cases
24/24
Protocol
25/25
Seeded MC
35/35
Python / web
129/129
Policy eval
0
Requirement failures

These counts summarize the current repository tree. Frozen completion and release reports keep the smaller Python-tool counts measured at their own commits; the repository reports and CI remain authoritative if the implementation evolves.

05Raspberry Pi target evidence

The completion campaign built and executed the portable core natively on Ubuntu 24.04 aarch64 with a Raspberry Pi kernel. The collection interface did not expose an authoritative board or SoC model, so the project does not guess one.

CampaignObserved resultScope
Native test run20/20 CTest suites passedPinned target campaign
Nominal timing250,000 ticks; 0 detected missesFaster-than-real-time process measurement
Controlled overrun99 expected misses detected in 100,000 ticksSynthetic overload every 1,000 ticks
Soak1,000,000 ticks; 0 detected missesPinned process/configuration

These are native target-execution and process measurements. They are not spacecraft hardware-in-the-loop, WCET, schedulability, hard-real-time qualification or operational reliability evidence.

Inspect the completion report and timing tables

Why the browser console exists

The interactive console is a recruiter-friendly way to exercise the documented state machine and fault responses. It models the behavior; it is not the native executable, a WebAssembly build, or a live Raspberry Pi process.

06Claim boundary

Demonstrated
  • Deterministic mode and FDIR behavior
  • Command integrity/freshness policy
  • Bounded recovery failure path
  • Requirement-to-test traceability
  • Repeatable fault and regression campaigns
  • Preserved Raspberry Pi execution evidence
Not established
  • DO-178C or certification compliance
  • Flight qualification / airworthiness
  • Hard-real-time WCET guarantees
  • Operational reliability
  • Cryptographic command authentication
  • Compatibility with spacecraft flight hardware

07What this project demonstrates

Software architecture: deterministic state machines, protocol boundaries, scheduling and event semantics.

Verification: testing normal behavior is only one layer; stale/replayed commands, simultaneous faults, recovery exhaustion and mutation/fuzz cases matter too.

Systems thinking: requirements are useful when they terminate in executable checks and reverse traceability can identify tests with no declared purpose.

Communication: the project distinguishes command authorization policy from cryptographic identity and hardware execution from real-time qualification.